8086 microprocessor-architecture

Architecture of 8086 

Ø  Intel 8086 is a 16-bit integer processor. It has 16-bit data bus and 20-bit address bus. Since 20-bit address lines are available, 8086 can access up to 2^20 or 1 Mega byte of physical memory.

Ø  The lower 16-bit address lines and 16-bit data lines are multiplexed (AD0 - AD15). 

Ø   It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode is suitable for system having multiple processors and Minimum mode is suitable for system having a single processor.

Ø   The architecture of 8086 is shown in fig.1.1 which is divided into two units,  (i) Bus Interface Unit (BIU)  (ii)  Execution Unit (EU). 

Bus Interface Unit (BIU)

Ø  The Bus Interface Unit (BIU) generates the 20-bit physical memory address and provides the interface with external memory (ROM/RAM). 

Ø   To speed up the execution, 6-bytes of instruction are fetched in advance and kept in a 6byte Instruction Queue while other instructions are being executed in the Execution Unit (EU). 

Ø   Hence after the execution of an instruction, the next instruction is directly fetched from the instruction queue without having to wait for the external memory to send the instruction. This is called pipe-lining and is helpful for speeding up the overall execution process.

Ø   There are four 16-bit segment registers, the code segment (CS), the stack segment (SS), the extra segment (ES), and the data segment (DS). 

Ø   These segment registers hold the corresponding 16-bit segment addresses. A segment address is the upper 16-bits of the starting address of that segment. The lower 4-bits of the starting address of a segment is always zero. The offset address is held by another 16bit register. 

Ø   The physical 20-bit address is calculated by shifting the segment address 4-bit left and then adding that to the offset address.

Ø  For Example:

                     Code segment Register CS holds the segment address which is 4569 H

                     Instruction pointer IP holds the offset address which is 10A0 H

                     The 20-bit physical address is calculated as follows.

                                   Segment address :    45690 H

                                   Offset address     : +  10A0 H 

                                   Physical address :    46730 H

Execution Unit (EU)

Ø  Execution unit gives instructions to BIU stating from where to fetch the data and then decode and execute those instructions. 

Ø   Its function is to control operations on data using the instruction decoder & ALU. EU has no direct connection with system buses as shown in the above fig.1, it performs operations over data through BIU.

 

 

ALU  

Ø  16-bit ALU performs all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations on 8-bit as well as 16-bit. 

General/Multipurpose Registers

 AX (accumulator)

Ø  16-bit AX register can be used as either of two 8-bit registers (AH and AL). 

Ø  The accumulator is used for instructions such as multiplication, division, and some of the adjustment instructions. 

Ø  The I/O instructions use the AX or AL for inputting / outputting 16 or 8 bit data to or from an I/O port.

 BX (base) 

Ø  16-bit BX register can be used as either of two 8-bit registers (BH and BL). 

Ø   BX register sometimes holds the offset address of a location in data segment.

CX (count)

Ø   16-bit CX register can be used as either of two 8-bit registers (CH and CL). 

Ø   CX register holds the count for various instructions. 

Ø   Instructions that use a count are the repeated string instructions (REP/REPE/REPNE); and shift, rotate, and LOOP/LOOPD instructions. 

Ø  The shift and rotate instructions use CL as the count, the repeated string instructions use CX, and the LOOP/LOOPD instructions use CX.

DX (data) 

Ø  16-bit DX register can be used as either of two 8-bit registers (DH and DL). 

Ø  DX register that holds a part of the result after multiplication or part of the dividend before division. 

Ø  DX register is used to contain I/O port address for I/O instruction

SI (source index)

Ø  The source index register often addresses source string data for the string instructions.

 DI (destination index) 

Ø  The destination index register often addresses destination string data for the string instructions.

BP (base pointer)

Ø  The base pointer points to a memory location for memory data transfers.

Special Purpose Registers 

Ø  The special-purpose registers include IP, SP and FLAGS and the segment registers include CS, DS, ES and SS.

IP (instruction pointer)  

Ø  IP addresses the next instruction in a section of memory defined as a code segment. 

Ø  The instruction pointer, which points to the next instruction in a program, is used by the microprocessor to find the next sequential instruction in a program located within the code segment. 

Ø   The instruction pointer can be modified with a jump or a call instruction.

SP (stack pointer)

Ø  SP addresses an area of memory called the stack. The stack memory stores data through this pointer with the instructions that address stack data.

 Flag Register

Ø  It is a 16-bit register as shown in fig.1.2 that changes its status according to the result stored after arithmetic or logical instruction executed. 

Ø  It has 9 flags and they are divided into 2 groups − Conditional Flags and Control Flags.

Ø  The rightmost five flag bits and the overflow flag change after many arithmetic and logic instructions are executed. These flags are called as Conditional Flags.

Ø   The flags never change for any data transfer or program control operation.

Ø  Interrupt, direction and trap flags are also used to control some features of microprocessor. These flags are called as Control Flags.

 C (carry flag): 

Ø  Carry holds the carry after addition or borrow after subtraction.

 P (parity flag): 

Ø  Parity is logic 0 for odd parity and logic 1 for even parity. Parity is the count of ones in a number expressed as even or odd. For example, if a number contains three binary one bits, it has odd parity. If a number contains no one bits, it has even parity.

 A (auxiliary carry flag):

Ø  The auxiliary carry holds the carry (half-carry) after addition or borrow after subtraction between bit positions 3 and 4 of the result. This flag bit is tested by the DAA and DAS instructions to adjust the value of AL after a BCD addition or subtraction.

  Z (zero flag): 

Ø  The zero flag shows that the result of an arithmetic or logic operation is zero. If Z = 1 , the result is zero; if Z = 0, the result is not zero.

  S (sign flag): 

Ø  The sign flag holds the arithmetic sign of the result after arithmetic or logic instruction executes. If S = 1, the sign bit (leftmost bit of a number) is set or negative; if S = 0, the sign bit is cleared or positive.

T (trap flag): 

Ø  It is used for single step control.

Ø   It allows user to execute one instruction of a program at a time for debugging.

Ø   When trap flag is set (T = 1), program can be run in single step mode.

 I (interrupt flag): 

Ø  The interrupt flag controls the operation of the INTR (interrupt request) input pin. If I = 1, the INTR pin is enabled; if I = 0, the INTR pin is disabled. The I flag bit is controlled by the STI (set I flag) and CLI (clear I flag) instructions.

 D (direction flag): 

Ø  The direction flag selects either the increment or decrement mode for the DI and/or SI registers during string instructions. If D = 1, the registers are automatically decremented; if D = 0, the registers are automatically incremented. 

Ø  The D flag is set with the STD (set direction) and cleared with the CLD (clear direction) instructions

O (overflow flag): 

Ø  Overflows occur when signed numbers are added or subtracted. An overflow indicates that the result has exceeded the capacity of the machine. 

Ø  For example, if 7FH (+127) is added using an 8-bit addition to 01H (+1), the result is 80H (–128). This result represents an overflow condition indicated by the overflow flag for signed addition. For unsigned operations, the overflow flag is ignored. 

Segment Registers

Ø  The complete 1Mbyte memory is divided into 16 logical segments. Each segment contains 64Kbyte of memory.

Ø  There are four segment registers in microprocessor which generate memory addresses when combined with other registers. 

CS (code) 

Ø  The code segment is a section of memory that holds the code (programs and procedures) used by the microprocessor. 

Ø  The code segment register defines the starting address of the section of memory holding code. 

Ø  CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions 

Ø  The code segment is limited to 64K bytes

  DS (data) 

Ø  The data segment is a section of memory that contains most data used by a program.

Ø   Data are accessed in the data segment by an offset address or the contents of other registers that hold the offset address. The length is limited to 64K bytes

 ES (extra) 

Ø  The extra segment is an additional data segment that is used by some of the string instructions to hold destination data.

SS (stack) 

Ø  The stack segment defines the area of memory used for the stack. The stack entry point is determined by the stack segment and stack pointer registers. 

Ø  The BP register also addresses data within the stack segment.